One of the most time consuming tasks in generating simulation models for a library of cells is timing characterization. A cell may be asked to operate with a wide range of output loading and input slew-rate conditions in a design. It requires a large number of simulations for each cell in the library to capture this information. Typically, each cell is simulated using a circuit level simulator a number of times, each with changes in the operating point for the cell. The resultant timing is measured from these simulations and then fit to an equation or curve(s) that represents the timing of the cell for a variety of differing operating conditions. The final accuracy of timing, or delays used in logic simulation depends on the quantity and the accuracy of the simulations, the resultant equation accuracy, and the ability to handle all aspects of these equations when calculating the final delays. Realize, that a typical library consisting of an excess of 150 cells, this process can be a formidable task. Gendel provides a means of reducing the complexity and number of simulations required to model delays of the library without sacrificing accuracy.
See our paper from Async94 Tools for Validating Asynchronous Digital Circuits for more information on how Gendel is used.